Epitaxy of SiGe and Other Compound Semiconductors

III-nitride devices are commonly made on sapphire substrates today for various commercial electronic and optoelectronic applications. Thus, this innovation relates directly to the combination of devices on opposite sides of the sapphire substrate. One possible device combination is to have LEDs one side and solar cells on the other, such as for displays.

This innovation is based on a new fabrication method that alleviates the thermal loading requirement of the substrate, which previously required surface temperatures within the range of 850 to 900C. Our method employs a new thermal loading requirement of sapphire substrate for growing single crystal SiGe on sapphire substrate, in the range of 450 to 500C. SiGe/sapphire wafers produced via this process show a high reflectivity without the discoloration that appears in low quality films.

Performance of solar cells and other electronic devices such as transistors can be improved greatly if carrier mobility is increased. Si and Ge have Type-II bandgap alignment in cubically strained and relaxed layers. Quantum well and super lattice with Si, Ge, and SiGe have been good noble structures to build high electron mobility layer and high hole mobility layers. However, the atomic lattice constant of Ge is bigger than that of Si and direct epitaxial growth generates large density of misfit dislocations which decrease carrier mobility and shorten device life time. So it required special buffer layers such as super lattice or gradient indexed layers to grow Ge on Si wafers or Si on Ge wafers. The growth of these buffer layers takes extra effort and time such as post-annealing process to remove dislocations by dislocation gliding inside buffer layer. This invention is a fabrication method for high mobility layer structures of rhombohedrally aligned SiGe on a trigonal substrate. The invention utilizes C-plane (0001) Sapphire which has a triangle plane, and a Si (Ge) (C) (111) crystal or an alloy of group TV semiconductor (111) crystal grown on the Sapphire.

Single Crystal SiGe semiconductors are viable via numerous advances patented by NASA. This includes the addition of a 1-2mm ring groove in the magnetron magnets which increases sputtering energy at 500C vs 800C, enabling thicker, faster deposition with better surface finish and consistent quality without heat soaking. The lack of thermal gradient removes inconsistencies in the product. SiGe can also utilize the CMOS manufacturing technique for additional cost savings and waste reduction. Further decreases to time investment for single crystal SiGe is made possible via reduced thermal load and soak temperatures, growing SiGe semiconductors on, conveniently, less expensive sapphire substrates. Crystal lattice matched growing methods to the sapphire substrate ensure defect-free SiGe production without interfacial dislocations. A graded indexed SiGe layer can be added to wafers grown in this lattice matched method, permitting thicker semiconductor growth without abrupt changes in strain build-up, carrier potential barrier, index of refraction change and bandgap at the interface. These advances provide improved semiconductor performance and quality with fewer defects in fabrication. The crystal alignment enables X-Ray diffraction identification of any defect location and density. It is also possible to also grow a Gallium Nitride or Indium Gallium Nitride layer on the opposite side of the Sapphire wafer, useful for solar capable LED display. A type II band-gap alignment of SiGe would result in highly efficient solar cells attaining 30% to 40% energy conversion efficiency. In addition to SiGe, the patented technology also covers these methodologies on tin-based or carbon-based semiconductors.

NASA Glenn's durable, extreme-temperature, integrated circuit chips begin with the replacement of conventional silicon IC transistors with n-channel SiC junction field effect transistors (JFET) and resistors that can reliably function above 500°C. JFETs with the necessary high-temperature stability and electrical gain are fabricated from commercial 4H-SiC wafers with epilayers using dry etching and a self-aligned n-type ion implantation. An innovative circuit approach creates digital logic gates from these normally-on n-channel JFETs and resistors. Using two levels of 500°C durable metal to interconnect numerous SiC gates, complex circuits enabling a variety of control, operation and sensing functions for intelligent systems in harsh environments can be implemented in physically small chips. The challenge of getting electrical signals to and from the chip in a harsh environment is overcome by the use of the iridium interfacial stack (IrIS) that acts simultaneously as a bond metal and diffusion barrier, and can be used on an ohmic contact to the SiC. Combined with Glenn-developed high-temperature durable ceramic chip packaging and harsh environment sensor technology, this revolutionary durable integrated circuit technology is game changing for harsh-environment applications of all types.