SpaceCube 3.0 Mini Processor Card
aerospace
SpaceCube 3.0 Mini Processor Card (GSC-TOPS-293)
A high-performance, spaceflight processor card designed to fit easily in a 1U CubeSat form factor system
Overview
SpaceCube 3.0 is a family of high-performance reconfigurable systems designed for spaceflight applications requiring on-board processing. Many proposed missions require next-generation, on-board processing capabilities to meet specified mission goals. Advanced laser altimeter, radar, lidar, and hyperspectral instruments are proposed for many upcoming missions, and all of these instrument systems will require advanced onboard processing capabilities to facilitate the timely conversion of science data into science information and data products. Both an order of magnitude increase in processing power and the ability to reconfigure on-the-fly are required to implement algorithms that detect and react to events, produce data products on-board for applications, enable sensor web multi-platform collaboration, and perform on-board lossless data reduction. The SpaceCube 3.0 Mini Processor Card is designed for the processing needs of emerging science missions.
The Technology
The SpaceCube 3.0 Mini Processor Card represents orders of magnitude increase in performance and capability over typical radiation-hardened processor-based systems and significant advances over the previous generation of SpaceCube technology. The primary processing engine of the card is a radiation-tolerant FPGA. This processor card is very low weight, can fit within the 1U CubeSat form-factor (10cm x 10cm x 10cm), and will be low power. Much of the SpaceCube 2.0 Micro design is incorporated into the SpaceCube 3.0 Mini design. In addition, lessons learned from the SpaceCube 2.0 Mini card are applied. Instead of using a rigid-flex design, the SC3.0 Mini uses a backplane architecture. The processor card plugs into a backplane that routes signals to other card slots. In order to meet the numerous high-speed I/O interfaces required by the latest generation science instruments and applications, a high-density backplane connector is needed. The SpaceCube 3.0 Mini uses a high-density connector to plug into the backplane. The FPGA has flash memory attached that is used for storing algorithm and application code for any hosted soft processors. The processor card also has a nanominiature front-panel connector that adds even more I/O to support instrument interfaces such as Camera Link or SpaceWire.
The SpaceCube 3.0 Mini Processor Card features a rad-tolerant FPGA, but the radiation mitigation can be tailored for harsher environments by adding an external rad-hard device that configures and monitors the FPGA over the backplane. The processor card pushes transceiver quantity, routing, and performance for spaceflight. The card is designed to fit in the compact 1U CubeSat form factor. The SpaceCube 3.0 Mini supports scalability by networking multiple processor cards together.
Benefits
- Smaller form factor
- Radiation hardened
- Greater bandwidth
- Enables networking with other SpaceCubes processor cards
Applications
- Satellite servicing
- Remote sensing
- Small satellite manufacturing
- Unmanned aerial vehicle manufacturing
Similar Results
SpaceCube 3.0 Flight Processor Card
SpaceCube 3.0 features the rad-tolerant multi-core T2080 processor and the rad-tolerant Kintex UltraScale FPGA. The SpaceCube 3.0 Flight Processor Card meets the industry standards in lightweight systems specifications. In addition, the flight processor card can be installed with an expansion card option to allow a tightly-coupled, mission unique card to be installed. The mission unique expansion card can support a variety of capabilities to make SpaceCube 3.0 a powerful instrument processor, including A/D converters, D/A converters, gigabit ethernet, and additional co-processors. Furthermore, the flight processor card is extremely flexible. Algorithms can be implemented in both the Kintex UltraScale FPGA and the T2080 processor. More sequential portions of the algorithm can be implemented quickly and efficiently on the processor, while other algorithms that are more parallel in nature and computation heavy can be accelerated in the FPGA. Using a hybrid system, each can be optimally implemented to take advantage of the features of both.
The SpaceCube 3.0 Flight Processor Card design consists mostly of NASA-qualified flight parts and has many features to mitigate radiation effects on the processor system. The processor card can configure the FPGA to scrub configuration memory. In addition, it can monitor the health of the processors, the FPGA, and any coprocessors on the expansion card using watchdog timers. The FPGA uses error detection and multiple redundant copies to mitigate against radiation upsets to the configuration files, which are stored in external non-volatile memories.
SpaceCube
Next generation instruments are capable of producing data at rates of 108 to 1011 bits per second, and both their instrument designs and mission operations concepts are severely constrained by data rate/volume. SpaceCube is an enabling technology for these next generation missions.
SpaceCube has demonstrated enabling capabilities in Earth Science, Planetary, Satellite Servicing, Astrophysics and Heliophysics prototype applications such as on-board product generation, intelligent data volume reduction, autonomous docking/landing, direct broadcast products, and data driven processing with the ability to autonomously detect and react to events. SpaceCube systems are currently being developed and proposed for platforms from small CubeSats to larger scale experiments on the ISS and standalone free-flyer missions, and are an ideal fit for cost constrained next generation applications due to the tremendous flexibility (both functional and interface compatibility) provided by the SpaceCube system.
Real-Time LiDAR Signal Processing FPGA Modules
The developed FPGA modules discern time-of-flight of laser pulses for LiDAR applications through the correlation of a Gaussian pulse with a discretely sampled waveform from the LiDAR receiver. For GRSSLi, up to eight cross-correlation engines were instantiated within a FPGA to process the discretely sampled transmit, receive pulses from the LiDAR receiver, and ultimately measure the time-of-flight of laser pulses at 20-picosecond resolution. Engine number is limited only by the resources within the FPGA fabric, and is configurable with a constant. Thus, potential time-of-flight measurement rates could go well beyond the 200-KHz mark required by GRSSLi. Additionally, the engines have been designed in an extremely efficient manner and utilize the least amount of FPGA resources possible.
SpaceCube Demonstration Platform
The HST SM4 SpaceCube flight spare was modified to create an experiment called the SpaceCube Demonstration Platform (SC DP) for use on the MISSE7 Space Station payload (in collaboration with NRL). It is designed to serve as an on-orbit platform for demonstrating advanced fault tolerance technologies.
With the use of Xilinx commercial Virtex4 FX60 FPGAs, the fault tolerant framework allows the system to recover from radiation upsets that occur in the rad-soft parts (Virtex4 FPGA logic, embedded PPCs in Virtex4 FPGAs, SDRAM and Flash), the C&DH system that runs simultaneously on both Virtex4 FPGAs that uses a robust telemetry packet structure, checksums, and the rad-hard service FPGA to validate incoming telemetry. The ability to be reconfigured from the ground while in orbit is a novel benefit, as well as is the onboard compression capabilities that allow compressed files from the ground to be uploaded to the SpaceCube.
Unique Datapath Architecture Yields Real-Time Computing
The DLC platform is composed of three key components: a NASA-designed field programmable gate array (FPGA) board, a NASA-designed multiprocessor on-a-chip (MPSoC) board, and a proprietary datapath that links the boards to available inputs and outputs to enable high-bandwidth data collection and processing.
The inertial measurement unit (IMU), camera, Navigation Doppler Lidar (NDL), and Hazard Detection Lidar (HDL) navigation sensors (depicted in the diagram below) are connected to the DLC’s FPGA board. The datapath on this board consists of high-speed serial interfaces for each sensor, which accept the sensor data as input and converts the output to an AXI stream format. The sensor streams are multiplexed into an AXI stream which is then formatted for input to a XAUI high speed serial interface. This interface sends the data to the MPSoC Board, where it is converted back from the XAUI format to a combined AXI stream, and demultiplexed back into individual sensor AXI streams. These AXI streams are then inputted into respective DMA interfaces that provide an interface to the DDRAM on the MPSoC board. This architecture enables real-time high-bandwidth data collection and processing by preserving the MPSoC’s full ability.
This sensor datapath architecture may have other potential applications in aerospace and defense, transportation (e.g., autonomous driving), medical, research, and automation/control markets where it could serve as a key component in a high-performance computing platform and/or critical embedded system for integrating, processing, and analyzing large volumes of data in real-time.
